1. Technical Field
The present invention is directed to a semiconductor device which has insulating regions formed in the semiconductor substrate on which the devices are formed. The present invention is also directed to a process for fabricating a semiconductor device in which the formation of these insulating regions is integrated with shallow trench isolation.
2. Art Background
Silicon-on-insulator (SOI) substrates have been offered as a solution to the problem of stray capacitance. The reduction in stray capacitance permits higher operating frequencies. SOI provides other advantages such as lower threshold voltage, minimum junction leakage, better packing density, borderless contacts, latch-up freedom and radiation hardness.
SOI circuits have been fabricated by forming a thin film of crystalline silicon on a layer of silicon dioxide that was formed on a semiconductor support wafer. Many methods have been proposed for forming such structures. Achieving a successful processing solution to forming an SOI substrate has been complicated because the thin silicon film is required to be crystalline silicon and must be less than about 200 nm thick in order to optimize the circuit performance. Another challenge has been making the thickness of this thin silicon film sufficiently uniform.
Another difficulty with current SOI is that the transistor body (i.e. substrate) connections are left to xe2x80x9cfloat.xe2x80x9d That is, the electrical potential at the interface between the silicon film and the insulator is not set to any fixed value. Consequently, the threshold voltage and other device parameters fluctuate randomly.
One method for fabricating an SOI MOS transistor is described in U.S. Pat. No. 5,891,763 to Wanless (Wanless hereinafter). In the Wanless process, a layer of silicon dioxide is formed on a single crystal silicon substrate. A layer of silicon nitride is formed over the layer of silicon dioxide. Windows are formed in the two-layer structure that define the location of the transistors. Silicon dioxide is grown in these windows, and windows are formed in that oxide layer. These windows later align with transistor channel locations. Amorphous silicon is then deposited over the resulting structure. The structure is then chemically-mechanically polished to remove the amorphous silicon outside the device areas. The amorphous silicon deposited in the window remains. The structure is annealed to convert the amorphous silicon to single-crystalline silicon. The windows formed in the insulating layer permit the transistor regions to be formed directly on the silicon substrate. The insulating layer is interposed between the regions other than the transistor regions and the semiconductor substrate.
A similar type of device is described in Kubota, T., et al., xe2x80x9cA New Soft-Error Immune DRAM Cell with a Transistor on a Lateral Epitaxial Silicon Layer,xe2x80x9d IEDM 87, Vol. 14.6, pp. 344-345 (1987). In this device, a transistor and a stacked capacitor are formed on a single substrate. Again, in this device, a layer of silicon dioxide is formed on a silicon substrate. A two-level cutout is formed in the layer of silicon dioxide. The upper level of the two-level cutout is wider than the lower level. The upper level defines the transistor area. A layer of silicon is then epitaxially formed on the structure, and the structure is then polished back so the only epitaxial silicon that remains is the silicon in the two-level cutout. The epitaxial silicon in the cutout is in contact with the silicon substrate on which the layer of silicon dioxide is formed. However, the insulator film is interposed between the stacked capacitor and the substrate.
The processes for making devices which have the advantages of the SOI substrate yet avoid the xe2x80x9cfloating bodyxe2x80x9d effect by allowing contact between the device silicon and the silicon substrate are complex in that they require complex lithography and etching steps in order to define windows of the desired dimension into the silicon dioxide layer. Lithography is required because there is currently no self-aligned technique for forming the windows through the silicon dioxide layer in relation to the device structures formed above the silicon dioxide layer. Accordingly, alternative processes for forming SOI transistors are sought.
The present invention is a process for fabricating a silicon-on-insulator (SOI) MOS transistor that is integrated with a process for shallow trench isolation. In the process of the present invention, shallow trench isolation is first performed on a silicon substrate. The shallow trench isolation process is well known to one skilled in the art. In the shallow trench isolation process, a pad oxide layer is formed on the silicon substrate. Over that pad oxide layer is formed a layer of material that serves as an etch stop for a subsequent chemical mechanical polishing step (e.g. silicon nitride, amorphous silicon, polycrystalline silicon, doped silicon oxide). It is advantageous if the etch stop layer is silicon nitride, because expedients for the subsequent removal of silicon nitride are more compatible with current processing than the expedients that are required to remove amorphous or polycrystalline silicon or doped silicon dioxide. By way of example, and not by limitation, the CMP stop layer is referred to herein as a silicon nitride layer. The combined thickness of the pad oxide and silicon nitride layer defines the combined thickness of the insulating islands subsequently formed on the substrate and the thickness of the single crystalline silicon formed over the insulating islands.
Trenches are formed in the silicon substrate with the dual-layer, pad oxide/silicon-nitride formed thereon. The depth of the trench is selected to define the depth of an insulating region that electrically isolates active surface portions of the integrated circuit formed on the silicon substrate from one another. The one or more different components of the circuit, such as transistors, capacitors, resistors and/or diodes, are formed in the different discrete portions and then electrically connected together by conductors on said active surface.
After the trenches are formed in the substrate, a layer of silicon dioxide is deposited over the substrate to fill the trenches. Conventional techniques such as TEOS (tetraethyl orthosilicate) of HDP (high density plasma) are contemplated as suitable for silicon dioxide layer. The silicon dioxide deposited on the surface of the silicon nitride layer is removed, and the silicon dioxide deposited in the trenches remains. Chemical mechanical polishing is a suitable expedient for removing the silicon dioxide. The silicon nitride layer serves as a stop layer for the chemical mechanical polishing step. In a conventional shallow trench isolation process, the silicon nitride and silicon dioxide layers are then removed from the substrate surface. In the present process, the silicon nitride and silicon dioxide layers are used in further processing.
The silicon nitride/silicon dioxide layer is then patterned to define the regions in the substrate in which the islands of insulating material are to be formed. The silicon nitride layer is patterned using standard lithographic techniques. In standard lithography for device fabrication, a pattern is formed in an energy-sensitive resist material that is formed on the silicon nitride layer. That pattern is then transferred into the underlying silicon nitride layer using a conventional etch expedient. The patterned layer of energy-sensitive material is then removed, leaving the patterned layer of silicon nitride on the substrate. The pattern has open regions through which the surface of the underlying substrate is exposed. These open regions define the placement of the islands of insulating material in the substrate.
The substrate is then subjected to an elevated temperature in an oxygen-containing atmosphere in order to oxidize the regions of silicon substrate exposed through the silicon nitride mask. The thickness of the silicon dioxide regions so formed selected to eliminate the junction leakage current from the devices subsequently formed over the insulating islands. Consequently, the thickness of the silicon dioxide as at least about 15 nm. This as-formed thickness ensures that, after subsequent processing, a thickness of at least about 5 nm remains. It is advantageous if the insulating regions also reduce or eliminate the junction capacitance of the devices subsequently formed over the islands of insulating material. In this regard it is advantageous if the islands of insulating material have a thickness of about 50 nm to about 100 nm.
The mask of silicon nitride and underlying pad oxide is then removed. The silicon underlying the mask is thereby exposed. Silicon is then epitaxially grown on the exposed silicon surfaces. Single crystal silicon is formed on the exposed silicon surfaces and over a small portion of the silicon dioxide islands adjacent to the exposed silicon surfaces. Single crystal silicon is otherwise not formed on the silicon dioxide insulating regions.
In order to form single crystal silicon over the silicon dioxide islands, amorphous silicon is deposited over the structure. The structure is then heated at a temperature and for a duration sufficient to recrystallize the amorphous silicon. The structure is then further processed to remove the amorphous silicon deposited and recrystallized over the silicon insulating regions and to planarize the substrate surface. Chemical mechanical polishing is one example of a suitable expedient for accomplishing this objective. The resulting structure has silicon dioxide insulating regions that separate active regions in the substrate. At least one active region has silicon dioxide islands formed beneath the single crystalline surface.
One advantage of the process of the present invention is that the insulating regions as well as the active regions above the insulating regions are self-aligned with the trench isolation regions. Consequently, complex lithography is not required to align the insulating regions with the trench isolation regions. In addition to avoiding the more complex lithographic alternative, the precise alignment of the trench isolation regions and the insulating regions provides for more efficient use of the surface area of the substrate. Since the current trend is to increase the number of devices per unit of substrate surface area, processes that permit more efficient use of the substrate surface area are desired. Also, the thickness of the active silicon region is defined by the height of the shallow trench isolation. Consequently, the thickness of the active silicon region is controllable and uniform for all of the devices. This enables the fabrication of an integrated circuit in which the device parameters (e.g., threshold voltage, dopant profiles, etc.) are both precise and consistent.